Published in

2017 IEEE International Solid-State Circuits Conference (ISSCC)

DOI: 10.1109/isscc.2017.7870432

Links

Tools

Export citation

Search in Google Scholar

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache

Proceedings article published in 2017 by Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai and other authors.
This paper was not found in any repository; the policy of its publisher is unknown or unclear.
This paper was not found in any repository; the policy of its publisher is unknown or unclear.

Full text: Unavailable

Question mark in circle
Preprint: policy unknown
Upload
Question mark in circle
Postprint: policy unknown
Upload
Question mark in circle
Published version: policy unknown
Upload
Beta version